1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having device isolation by STI and its manufacturing method.
2. Related Background Art
For the purpose of downsizing semiconductor devices, the method of isolating devices by STI (Shallow Trench Isolation) has been used for years in lieu of the technique using selective oxidation for isolating devices. STI is a technique for electrically insulating device regions forming devices from other regions in a semiconductor device by making trenches. In STI, trenches are formed in device isolating regions instead of selective oxidation thereof.
FIG. 8 is an enlarged cross-sectional view of a semiconductor device 700 having conventional STI under a process of its manufacturing. A gate insulating film 20 is formed on the top surface of a semiconductor substrate 10. A gate electrode 30 in form of an amorphous silicon film overlies the gate insulating film 20. A silicon nitride film 40 is deposited on the gate electrode 30. A silicon oxide film 50 is deposited on the silicon nitride film 40.
The silicon nitride film 40 and the silicon oxide film 50 are selectively removed by etching into a predetermined pattern by photolithography. After that, using the silicon oxide film 50 as a mask, the gate electrode 30, the gate insulating film 20 and the semiconductor substrate 10 are selectively removed by etching. In this etching, the trench 60 is formed to dig into the semiconductor substrate 10.
Subsequently, the side and bottom surface portions of the trench 60 are oxidized by RTO (rapid thermal oxidation) in an oxygen O2 atmosphere held at 1000° C. In FIG. 8, the trench 60 and the surrounding structure after RTO treatment are shown in an enlarged scale.
On the side surface and the bottom surface of the trench 60, a silicon oxide film 70 is formed by RTO. The silicon oxide film 70 protects the semiconductor substrate 10, etc.
In general, the diffusion coefficient of an oxidation seed is smaller when diffusing into silicon single crystal used as a semiconductor substrate exhibit than when diffusion into amorphous silicon.
Therefore, in the oxidation process by RTO, thickness T2 of the silicon oxide film 70b formed on silicon single crystal used as the semiconductor substrate 10 is thinner than the thickness T1 of the silicon oxide film 70a formed on the gate electrode 30.
Either in silicon single crystal or amorphous silicon, end portions like sides or corners located at boundaries of two planes receive a larger stress than flat surface portions as the oxidation progresses. To such end portions of silicon single crystal or amorphous silicon, the oxide seed is difficult to diffuse. Therefore, there occurs the phenomenon in which planar surfaces of silicon single crystal or amorphous silicon are more easily oxidized whereas end portions of that are difficult to oxidize.
FIG. 2B is an enlarged cross-sectional view of an end portion of a semiconductor substrate and an end portion of a gate electrode that are encircled by a broken line circle in FIG. 8. Since the end. portion of the semiconductor substrate 10 and the end portion of the gate electrode 30 are more difficult to oxidize than flat surfaces, the oxide film formed on the semiconductor substrate 10 and the gate electrode 30 become thinner and thinner toward their end portions than the thickness on their flat surfaces. As a result, the end portion of the semiconductor substrate 10 and the end portion of the gate electrode 30 are sharpened (see the inside of the broken line circle of FIG. 2B). The shaper the end portions of the semiconductor substrate 10 and the gate electrode 30, the larger the stress applied thereto. Thus the electric field is liable to concentrate at the end portions.
In addition, since the silicon oxide film 70b is thinner than the silicon oxide film 70a, the end portion of the gate electrode 30 overlaps a flat portion of the substrate top surface 12 when viewed from a vertical direction relative to the substrate top surface 12 of the semiconductor substrate 10 (see the dot-and-dash line in FIG. 2B).
As the stress to the gate electrode 30 and the gate insulating film 20 becomes larger, electrons trapped in the gate insulating film 20 increase (hereinafter called trapped electrons). The increase of the trapped electrons causes fluctuation of the threshold voltage (see FIG. 6).
Fluctuation of the threshold voltage prevents normal operation of the semiconductor device 700. In case the gate electrode 30 is used as the floating gate electrode of a memory, those defects often decreases the possible frequency of write and erase operation (hereinafter called W/E endurance characteristics) (see FIG. 7).
Furthermore, when viewed from a direction vertical to the substrate top surface 12 of the semiconductor substrate 10, since the end portion of the gate electrode 30 liable to gather the electric field overlaps a flat portion of the substrate top surface 12, the resistance voltage of the gate in the semiconductor device 700 undesirably decreases.